(1) Field of the Invention
The present invention relates to a debugging mechanism and, more particularly, to an analysis technique for use in debugging of an operation of a system having a plurality of bus masters.
(2) Description of the Related Art
In a recent system LSI, a plurality of bus masters are integrated on one LSI and share a common bus slave (e.g., a memory) in many cases. Therefore, enhancement in performance of bus access is indispensable in order to enhance not only operational performance of each bus master but also performance of an entire system.
In order to achieve the aforementioned enhancement, there are generally employed release control for write access and out of order control for bus access, as disclosed in JP3027439B. In the out of order control, consistency of an access request occurrence order and a bus access execution order is not ensured between different bus masters. Consequently, if a plurality of bus masters share a common bus slave as system specifications, synchronization between bus masters in an out of order relation must be ensured in some way. This synchronization tends to be ensured by software processing.
However, there is only software corresponding to debugging specialized for a specific bus master in a conventional software development environment. Such software is lacking in the function of debugging including a system operation of another bus masters. Therefore, it is difficult to perform debugging itself heretofore.